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NEURAL NETWORK BASED PERFORMANCE ESTIMATION METHODOLOGY OF FPGA FPU IP’S FOR THE DESIGNS WITH HIGH PERFORMANCE REQUIRE...
ISSN: 2757 - 9093
Publisher: author
NEURAL NETWORK BASED PERFORMANCE ESTIMATION METHODOLOGY OF FPGA FPU IP’S FOR THE DESIGNS WITH HIGH PERFORMANCE REQUIRE...
Indexed in
Technology and Engineering
ARTICLE-FACTOR
1.3
Article Basics Score: 3
Article Transparency Score: 3
Article Operation Score: 3
Article Articles Score: 2
Article Accessibility Score: 2
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International Category Code (ICC):
ICC-1802
Publisher: Fenerbahce University Journal Of Design, Architecture And ..
International Journal Address (IAA):
IAA.ZONE/275795799093
eISSN
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2757 - 9093
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Abstract
In applications requiring high precision calculations, floating point number representation is preferred instead of fixed point number representation system. The main reason is that floating point number representation can express numbers in a much wider range. Since the design of floating point arithmetic processing units is a difficult process, the use of floating point units provided by FPGA design companies (such as Xilinx, Intel) can be preferred for arithmetic operations involving floating point in an algorithm design process on an FPGA. In case the use of IPs offered by FPGA manufacturers is preferred, the area usage and maximum frequency parameters of these IPs are not predicted before design. This situation raises the need to obtain floating point units that give the maximum frequency with the minimum area, especially when there is a requirement to maximize the output of the system. However, it is necessary to wait for minute...
